At present, in design of liquid crystal panel of mobile products, a shift register circuit capable of accomplishing bi-directional scanning has been widely used as a gate driving circuit and is integrated on an array substrate to achieve scanning and driving the panel, such that the cost may be saved and a design with two symmetric sides may be achieved for the panel. In addition, bonding area and fan-shaped wiring space for a gate circuit control chip may be omitted, such that a narrow frame design may be achieved, meanwhile a bonding process in the direction of gate may be omitted, which is advantageous for increasing the productivity and yield rate.
The bi-directional scanning shift register circuit includes a shift register unit circuit in a first row, a shift register unit circuit in a last row, and at least one shift register unit circuit in a middle row. A practicable shift register unit circuit in the first row is shown in FIG. 1a and includes ten Thin Film Transistors and a capacitor, wherein a frame start signal (STV) input terminal is connected to a signal input terminal (INPUT). A shift register unit circuit in the last row is shown in FIG. 1b, which is matched with the shift register unit circuit in the first row as shown in FIG. 1a and includes ten Thin Film Transistors and a capacitor, a frame start signal input terminal is connected to a signal reset terminal (RESET). A shift register unit circuit in a middle row is shown in FIG. 1c, which is matched with the shift register unit circuit in the first row as shown in FIG. 1a and the shift register unit circuit in the last row as shown in FIG. 1b and includes ten Thin Film Transistors and a capacitor.
When a forward scanning is performed, as shown in FIG. 1d, an output signal of a shift register unit in a current row is used as an input signal of a shift register unit in a next row, and an output signal of the shift register unit in the next row is used as a reset signal of the shift register unit in the current row for resetting the shift register unit in the current row. When a reverse scanning is performed, as shown in FIG. 1e, the output signal of the shift register unit in the next row is used as an input signal of the shift register of the current row, and the output signal of the shift register unit in the current row is used as a reset signal of the shift register unit in the next row for resetting the shift register unit in the next row. A timing waveform for the forward scanning is as shown in FIG. 1f, in the forward scanning, when the frame start signal is at a high level, a forward clock signal (CLK) changes from a low level to a high level, the output terminal outputs a pulse of the forward clock signal; A timing waveform for the reverse scanning is as shown in FIG. 1g, in the reverse scanning, when the frame start signal is at a high level, a reverse clock signal (CLKB) changes from a low level to a high level, the output terminal outputs a pulse of the reverse clock signal.
However, when the forward clock signal or the reverse clock signal changes from the low level to the high level, if the frame start signal is also at the high level, it tends to pull up the level at a node PU (pull up node) in FIG. 1a, FIG. 1b and FIG. 1c. As shown in FIG. 1h, since a size of a Thin Film Transistor TFT M01 is large, there is a large parasitic capacitance C02, and before the forward clock signal becomes the high level, the node PU keeps in the low level, as shown in FIG. 1i; when the frame start signal is at the high level, the forward clock signal changes from the low level to the high level, the node PU also becomes the high level due to the parasitic capacitance of TFT M01, such that there occurs a little swell in the waveform of the node PU, also a little swell occurs in the output signal due to an coupling effect of a capacitor C01, such that a H-line defect is generated on a display screen.